A memory controller controls access to and from one or more memory module(s), such as dynamic random access memory (DRAM), SDRAM and DDR-SDRAM. A sequencer core within the memory controller issues commands to either control, read or write to the memory module. In the case of a write transaction, the sequencer core issues a command to write data at a particular address. The command to write, the data, and the address are transmitted to the memory module, and the memory module writes the data to the address.
In the case of a read transaction, the sequencer core issues a command to read data at a particular address in the memory module. When the memory module is DDR-SDRAM, unlike the case of a write transaction, after sending the command to read an address, the memory controller requires a response from the memory module. The response includes the data stored at the address.
The response from the memory module can require a variable amount of time. When the memory module responds to a read request, the memory module transmits the data at the address, with a data strobe signal (DQS). The DQS indicates to the receiving memory controller that the data is transmitted. In response to receiving the DQS signal, the memory controller reads the incoming data and stores the data into a read data queue by registering data on the rising and falling edges of DQS.
The DQS is typically a voltage pulse with a predetermined voltage and width. The memory controller detects the DQS by comparing a signal to a predetermined threshold. The threshold is usually a proportion of the voltage. When the signal exceeds the threshold, the memory controller detects the rising edge of DQS and when the signal falls below the threshold, falling edge of DQS is detected.
The memory controller and the memory module are typically implemented as separate integrated circuits. The integrated circuits are fused to a motherboard and conduct read and write transactions over a printed circuit, connecting the memory module and the memory controller.
Printed circuits are susceptible to noise signals. Noise signals can be caused by a number of different factors, such as cross-talk, simultaneous switching noise and ground bounce. If the magnitude of the noise signals exceed the predetermined voltage, the memory controller might erroneously detect a transition on DQS and read erroneous signals as data.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.